Nowadays, as electronic devices are getting smaller in size and lighter in weight, as represented by a portable device or a mobile device, a semiconductor package used for them is also required to be smaller in size and lighter in weight.
In order to satisfy the demand, a semiconductor package having approximately the same size as a semiconductor chip (hereinafter referred to as a chip), namely a CSP (Chip Size Package) appears and comes into practical use.
Now, the mainstream form of the CSP is a face-up structure using a wire bonding technique. In the CSP, however, after mounting the chip on a substrate called as an interposer, wire bonding is carried out between a wire bonding terminal on the interposer, which is located outside the chip mounted section and an electrode pad on the chip. This makes the chip size a little larger than the size of the semiconductor package.
For this reason, technique called a wafer level CSP is now attracting attention, which can be further smaller in size and lighter in weight than the CSP of the wire bonding type, can be packaged in a same size as the chip size, and can be manufactured more inexpensively.
Tokukaihei No. 10-261663 (publication date: Sep. 29, 1998) discloses a structure and a manufacturing method of the wafer level CSP. FIG. 7 shows a semiconductor device 113 to which the technique in the publication is applied. The diagram is a vertical sectional view showing a part of the semiconductor device 113 having a plurality of external connecting terminals 110.
In the semiconductor device 113, a first insulation layer 103 is formed on a semiconductor substrate 101 having a plurality of electrode pads 102. The first insulation layer 103 is composed of an inorganic insulation layer 103a and an organic insulation layer 103b. 
The first insulation layer 103 is partly eliminated to form a first opening section 103c, thereby exposing the electrode pad 102. The electrode pad 102 is connected with the external connecting terminal 110 via a leading wiring layer 112. One terminal of the leading wiring layer 112 is connected on the electrode pad 102, whereas the other terminal is connected with the external connecting terminal 110.
The leading wiring layer 112 is composed of a first barrier metal layer 105, a main conductor layer 106 and a second barrier metal layer 107. The first barrier metal layer 105 covers a bottom surface of the main conductor layer 106, while the second barrier metal layer 107 covers a top surface of the main conductor layer 106.
On the first insulation layer 103, a second insulation layer 109 is provided so as to cover side and top surfaces of the leading wiring layer 112. The second insulation layer 109 includes a second opening section 109b where the external connecting terminal 110 is provided.
A material for the first barrier metal layer 105 is required to be metal having high adhesion to the organic insulation layer 103b, because low adhesion causes lower reliability of the semiconductor device 113.
A material for the main conductor layer 106 is required to be metal having high conductivity, in order to reduce resistance of the whole leading wiring layer 112.
A material for the second barrier metal layer is required to be metal having high hardness, so as to protect the semiconductor substrate 101 from breaking when a wire (not shown) is connected to the external connecting terminal 110.
As described above, in the leading wiring layer 112, since the second barrier metal layer 107 and the first barrier metal layer 105 are formed on the top and bottom surfaces of the main conductor layer 106 having high conductivity, namely low resistance, it is possible to restrain electromigration of the second insulation layer 109 and the first insulation layer 103.
However, in the conventional arrangement, as shown in FIG. 7, exposure of side surfaces of the main conductor layer 106 causes a problem that electromigration occurs with the second insulation layer 109 on side surfaces of the leading wiring layer 112.
Furthermore, during a manufacturing step of the semiconductor device 113, the main conductor layer 106 and the second insulation layer 109 have low adhesion, thereby causing a problem that the reliability of the semiconductor device 113 is lowered.
For trying to solve the problems, the publication discloses a semiconductor device in which side surfaces of the main conductor layer 106 are also covered with the second barrier metal layer 107. FIGS. 8(a) to 8(e) outline its manufacturing method.
Note that, for convenience, the same reference numerals are assigned to members which have same functions as those used in FIG. 7, and thus their explanation is omitted.
First, as shown in FIG. 8(a), the inorganic insulation layer 103a and the organic insulation layer 103b are formed on the semiconductor substrate 101 having a semiconductor element (not shown) and the plurality of electrode pads 102, and then the first opening section 103c is formed on the electrode pads 102. Next, the first barrier metal layer 105 is formed by sputtering or evaporation.
Next, a resist 201 is formed on the first barrier metal layer 105, and then the resist 201 is exposed and developed, thereby eliminating the resist 201 in an area where the leading wiring layer 112 (see FIG. 7) is formed.
Because of this, as shown in FIG. 8(b), the resist 201 remains only in areas where wiring is not formed. Next, as shown in FIG. 8(c), the main conductor layer 106 is formed by an electrolytic plating (electric plating) method or an electroless plating method.
Here, heating at 150° C. contracts the resist 201, thereby providing a space between the main conductor layer 106 and the resist 201, as shown in FIG. 8(d). Next, as shown in FIG. 8(e), the second barrier metal layer 107 is formed by the electrolytic plating method or the electroless plating method.
After that, the resist 201 is eliminated, and the first barrier metal layer 105 is etched with using the second barrier metal layer 107 and the main conductor layer 106 as masks, thereby forming the leading wiring layer 202.
Because of this, since the second barrier metal layer 107 or the first barrier metal layer 105 is formed on the respective side, top, and bottom surfaces of the main conductor layer 106 having high conductivity, it is possible to restrain electromigration of the second insulation layer 109 (see FIG. 7) and the first insulation layer 103.
In the method of contracting the resist 201 as described above, however, even though an upper portion of the resist 201 is contracted, due to adhesion to the first barrier metal layer 105, a lower portion of the resist 201 is difficult to be contracted, or only possibly contracted a very small amount.
Therefore, on lower portions of the side surfaces of the main conductor layer 106, the barrier metal layer is not plated, or only plated very thinly, thus leaving reliability of the leading wiring layer 202 low.